Formation of a single-crystal Si semiconductor layer on an insulator is widely known as a silicon on insulator SOI. This technique has been extensively researched since a device utilizing the SOI technique has a number of advantages which cannot be achieved by a bulk Si substrate forming the normal Si integrated circuit. Specifically, for example, the following advantages can be achieved by employing the SOI technique:
1. Dielectric isolation is easy and high integration is possible;
2. Radiation resistance is excellent;
3. Floating capacitance is reduced and high speed is possible;
4. Well process can be prevented;
5. Latch-up can be prevented; and
6. Fully depleted (FD) field effect transistor is achieved through film thickness reduction.
These are described in detail, for example, in the literature of Special Issue: "Single-crystal silicon on non-single-crystal insulators"; edited by G. W. Cullen, Journal of Crystal Growth, volume 63, no. 3, pp. 429-590 (1983).
Further, over the past few years, the SOI has been largely reported as a substrate which realizes the acceleration of a MOSFET and low power consumption (IEEE SOI conference 1994). Since an element has an insulating layer at its lower part when employing the SOI structure, an element separation process can be simplified as compared with forming an element on a bulk silicon wafer so that preparing a device can take less time. Specifically, in addition to achieving the higher performance, reduction of the wafer cost and the process cost is expected as compared with a MOSFET or IC on bulk silicon.
Particularly, the fully depleted (FD) MOSFET is expected to achieve higher speed and lower power consumption through improvement in driving force. In general, a threshold voltage (Vth) of a MOSFET is determined by the impurity concentration at a channel portion. On the other hand, in case of the FD MOSFET using the SOI, a depletion layer is also subjected to an influence of a film thickness of the SOI. Thus, for producing the large scale integrated circuits at high yield, uniformity of the SOI thicknesses has been strongly demanded.
On the other hand, a device on a compound semiconductor has high performance, such as, high speed and luminescence, which cannot be achieved by Si. Presently, such a device is normally formed in an epitaxial layer grown on a compound semiconductor substrate, such as a GaAs substrate.
However, there is a problem that the compound semiconductor substrate is expensive while low in mechanical strength, so that a large area wafer is difficult to produce.
Under these circumstances, an attempt has been made to achieve the heteroepitaxial growth of a compound semiconductor on a Si wafer which is inexpensive and high in mechanical strength so that a large area wafer can be produced.
Referring back to the SOI, research on the formation of the SOI substrates has been active since the 1970s. In the beginning, the research was performed in connection with the SOS (sapphire on silicon) method, which achieves the heteroepitaxial growth of single-crystal silicon on a sapphire substrate being an insulator, the FIPOS (fully isolated by porous oxidized silicon) method, which forms the SOI structure by dielectric isolation based on oxidation of porous Si, and the oxygen ion implantation method.
In the FIPOS method, an n-type Si layer is formed on a surface of a p-type Si single-crystal substrate in an island shape through the proton ion implantation (Imai and collaborator, J. Crystal Growth, vol. 63, 547 (1983)) or through the epitaxial growth and the patterning, then only the p-type Si substrate is rendered porous so as to surround the Si island from the surface by means of the anodizing method in a HF solution, and thereafter the n-type Si island is dielectric-isolated through accelerating oxidation. In this method, there is a problem that the isolated Si region is determined in advance of the prepared device so that the degree of freedom of device designing is limited.
The oxygen ion implantation method is a method called SIMOX first reported by K. Izumi. After implanting about 10.sup.17 to 10.sup.18 /cm.sup.2 of oxygen ions into a Si wafer, the ion-implanted Si wafer is annealed at the high temperature of about 1,320.degree. C. in the atmosphere of argon/oxygen. As a result, oxygen ions implanted with respect to a depth corresponding to a projection range (Rp) of ion implantation are bonded with silicon so as to form a silicon oxide layer. On this occasion, a silicon layer which has been rendered amorphous at an upper portion of the silicon oxide layer due to the oxygen ion implantation is also recrystallized so as to be a single-crystal silicon layer. Conventionally, there have been a lot of defects included in the silicon layer on the surface, that is, about 10.sup.5 /cm.sup.2. On the other hand, by setting an implantation amount of oxygen to about 4.times.10.sup.17 /cm.sup.2, defects are successfully reduced to about 10.sup.2 /cm.sup.2. However, since the ranges of implantation energy and implantation amount for maintaining the quality of the silicon oxide layer, the crystalline property of the surface silicon layer and the like are so narrow that thicknesses of the surface silicon layer and the buried silicon oxide (BOX: buried oxide) layer were limited to particular values. For achieving a desired thickness of the surface silicon layer, it was necessary to perform sacrificial oxidation and epitaxial growth. In this case, there is a problem that, since the degradation caused through these processes is superimposed on the distribution of thicknesses, the thickness uniformity deteriorates.
It has been reported that a formation failure region of silicon oxide called a pipe exists in the BOX layer. As one cause of this, the forcing matter upon implantation, such as dust, is considered. In the portion where the pipe exists, the deterioration of the device characteristic results from leaks between an active layer and a support substrate.
Further, since the amount of ion implantation in the SIMOX is large as compared with the ion implantation in the ordinary semiconductor process, implantation time is lengthy even after developing the apparatus to be used exclusively for that process. The ion implantation is performed by raster-scanning an ion beam of a given current amount or expanding the beam so that an increment of the implantation time is predicted following an increment in the area of the wafer. Further, in the high temperature heat treatment of the large-area wafer, it has been pointed out that a problem of occurrence of slip due to the temperature distribution in the wafer becomes more severe. In SIMOX, the heat treatment is essential at high temperature, that is, 1,320.degree. C., which is not normally used in silicon semiconductor processes, so that there has been concern that this problem, including the development of the apparatus, becomes more significant. On the other hand, apart from the foregoing conventional SOI forming method, attention has been recently given to the method which forms the SOI structure by sticking a Si single-crystal substrate to a thermal-oxidized Si single-crystal substrate through heat treatment or using adhesives. In this method, it is necessary to form an active layer for the device into a uniform film. Specifically, it is necessary to form a Si single-crystal substrate of a thickness of as much as hundreds of microns into a film of several microns or less. There are three kinds of methods for thickness reduction as follows:
1. Thickness reduction through polishing;
2. Thickness reduction through local plasma etching;
3. Thickness reduction through selective etching.
In polishing, uniform thickness reduction is difficult. Particularly, in the case of thickness reduction to submicrons, the irregularity amounts to as much as tens of percents so that uniformity is a big problem. If the size of the wafer is further enlarged, the difficulty is increased correspondingly.
In the second method, after reducing the thickness to about 1 to 3 .mu.m through polishing, the thickness distribution is measured at many points. Thereafter, by scanning the plasma using the SF6 of a diameter of several millimeters based on the thickness distribution, etching is performed while correcting the thickness distribution, to reduce the thickness to a given value. In this method, it has been reported that the thickness distribution can be within the range of about .+-.10 nm. However, if foreign matter (particles) exists on the substrate upon plasma etching, the foreign matter works as an etching mask so that projections are formed on the substrate.
Since the surface is rough immediately after the etching, touch polishing is necessary after completion of the plasma etching. The polishing amount is controlled based on time management, and hence, the control of final film thickness and the deterioration of film thickness distribution due to polishing have been noted. Further, in polishing, abrasives such as colloidal silica directly rub the surface working as an active layer so that there has been concern about formation of a fracture layer due to polishing and introduction of processing distortion. Further, if the wafer is substantially increased in area, since the plasma etching time is increased in proportion to increment of the wafer area, there is concern about extreme reduction of the throughput.
In the third method, a film structure capable of selective etching is formed in advance in a substrate to be formed into a film. For example a p+-Si thin layer containing boron in the concentration no less than 10.sup.19 /cm.sup.3 and a p.sup.- -Si thin layer are formed on a p.sup.- substrate using the method of, for example, the epitaxial growth to form a first substrate. The first substrate is bonded with a second substrate via an insulating layer such as an oxide film, and then the underside of the first substrate is ground or polished in advance so as to reduce its thickness. Thereafter, the p.sup.+ layer is exposed through the selective etching of the p.sup.- layer and further the p.sup.- layer is exposed through the selective etching of the p.sup.+ layer, so as to achieve the SOI structure. This method is detailed in the report of Maszara.
Although the selective etching is said to be effective for uniform thickness reduction, it has the following problems:
The ratio of etching selectively is 10.sup.2 at most, which is not sufficient.
Since surface property after etching is bad, touch polishing is required after etching. However, as a result, the film thickness is reduced and the thickness uniformity tends to deteriorate. Particularly, although the amount of polishing is managed based on time, since dispersion of the polish speed is large, the control of the amount of polishing is difficult. Thus, it becomes a problem particularly in forming an extremely thin SOI layer of, for example, 100 nm.
The crystalline property is bad because of using the ion implantation, the epitaxial growth or the heteroepitaxial growth on the high-concentration B doped Si layer.
The surface property of a surface to be bonded which is inferior to the normal silicon wafer (C. Harenda, et al., J. Elect. Mater. Vol. 20, 267 (1991), H. Baumgart, et al., Extended Abstract of ECS 1st International Symposium of Wafer Bonding, pp. 733 (1991), C. E. Hunt, Extended Abstract of ECS 1st International Symposium of Wafer Bonding, pp. 696 (1991)). Further, the selectivity of selective etching largely depends upon a difference in concentration of impurities such as boron and sharpness of the profile in the depth direction. Accordingly, if the high-temperature bonding annealing for increasing the bonding strength or the high-temperature epitaxial growth for improving the crystalline property is performed, the depth direction distribution of the impurity concentration expands so that the selectivity of etching deteriorates. That is, it is difficult to improve both the ratio of etching selectively and the crystalline property or the bonding strength.
Recently, in view of the foregoing problems, Yonehara and collaborators have reported the bonded SOI which is excellent in thickness uniformity and crystalline property and capable of batch processing. Brief explanation about this will be given using FIGS. 6A to 6E. In this method, a porous layer 62 formed on an Si substrate 61 is used as a material for selective etching (FIG. 6A). After epitaxially growing a non-porous single-crystal Si layer 63 on the porous layer 62 (FIG. 6B), the three-layer composite is bonded with a support substrate 64 via the oxidized Si layer 63 (FIG. 6C). The Si substrate 61 is reduced in thickness through grinding or the like from the underside so as to expose the porous Si 62 all over the substrate (FIG. 6D). The exposed porous Si 62 is removed through etching using a selective etching liquid, such as, KOH or HF+H.sub.2 O.sub.2 (FIG. 6E). At this time, since the ratio of etching selectively porous Si relative to bulk Si (non-porous single-crystal silicon) can be set fully high, that is, 100,000 times, the non-porous single-crystal silicon layer grown on the porous layer in advance can be left on the support substrate without being hardly reduced in thickness, so as to form the SOI substrate. Accordingly, the thickness uniformity of the SOI is substantially determined during the epitaxial growth. since a CVD apparatus used in the normal semiconductor process can be used for the epitaxial growth, according to the report of Sato and collaborator, the thickness uniformity is realized, for example, within 100 nm.+-.2%. Further, the crystalline property of the epitaxial silicon layer is also excellent and has been reported to be 3.5.times.10.sup.2 /cm.sup.2.
In the conventional method, since the selectivity of etching depends on the difference in impurity concentration and the depth direction profile, the temperature of the heat treatment (bonding, epitaxial growth, oxidation or the like) which expands the concentration distribution is largely limited to approximately no higher than 800.degree. C. On the other hand, in the etching of this method, since the difference in structure between porous and bulk determines the etching speed, the limitation of the heat treatment temperature is small. It has been reported that the heat treatment at about 1,180.degree. C. is possible. For example, it is known that the heat treatment after bonding enhances the bonding strength between the wafers and reduces the number and size of voids generated at the bonded interface. Further, in the etching based on such a structural difference, the particles, even if adhered on porous silicon, do not affect the thickness uniformity.
On the other hand, in general, on a light transmittable substrate, typically glass, the deposited thin Si layer only becomes amorphous or polycrystalline at best, reflecting disorder in crystal structure of the substrate, so that the high-performance device cannot be produced. This is due to the crystal structure of the substrate being amorphous, and thus an excellent single-crystal layer cannot be achieved even by merely depositing the Si layer.
However, the semiconductor substrate obtained through bonding normally requires two wafers one of which is removed, wastefully for the most part, through polishing, etching or the like, so that the finite resources of the earth are wasted.
Accordingly, in the conventional method, the bonded SOI has various problems of controllability, uniformity and economics.
A method is proposed in Japanese Patent Application No. 7-045441 for recycling the first substrate which is wasted in such a bonding method.
In this method, the following method is adopted, in the foregoing bonding and etch-back method using the porous Si, instead of the step for reducing in thickness the first substrate through grinding, etching or the like from the underside so as to expose the porous Si. This will be explained using FIGS. 7A to 7E.
After forming porous a surface layer 72 of an Si substrate 71 (FIG. 7A), a single-crystal Si layer 73 is formed thereon (FIG. 7B). Then, the single-crystal Si layer 73 along with the Si substrate 71 is bonded to a main surface of another Si substrate 74, working as a support substrate, via an insulating layer therebetween (FIG. 7C). Thereafter, the bonded wafers are separated at the porous layer 72 and the porous Si layer 72 exposed on the surface at the side of the Si substrate 74 is selectively removed so that the SOI substrate is formed. Separation of the bonded wafers is performed, for example, a method selected from the following methods that the tensile force or pressure is sufficiently applied to the bonded wafers perpendicularly relative to an in-plane and uniformly over in-plane; that the wave energy such as the ultrasonic wave is applied; that the porous layer is exposed at the wafer end surfaces, the porous Si is etched to some extent, and what is like a razor blade is inserted thereinto; that the porous layer is exposed at the wafer end surfaces and a liquid such as water is impregnated into the porous Si, and the whole bonded wafers are heated or cooled so as to expand the liquid. Alternatively, separation is performed by applying the force to the Si substrate 71 in parallel to the support substrate 74.
Each of these methods is based on the fact that, although the mechanical strength of the porous Si layer 72 differs depending on the porosity, it is considered to be much weaker than the bulk Si. For example, if the porosity is 50%, the mechanical strength can be considered to be half the bulk. Specifically, when a compressive, tensile or shear force is applied to the bonded wafers, the porous Si layer is first ruptured. As the porosity is increased, the porous layer can be ruptured with a weaker force.
However, if the porosity of porous silicon is increased, it is possible that distortion is introduced due to the ratio of bulk silicon relative to the lattice constant being increased so as to increase warpage of the wafer. As a result, the following problems may be raised, that is, the number of void bonding failure regions, called voids is increased upon bonding, the crystal defect density is increased and, in the worst case, cracks are introduced into the epitaxial layer, and slip lines are introduced on the periphery of the wafer due to the influence of thermal distortion upon the epitaxial growth.
When applying the force in the vertical or horizontal direction relative to the surface of the wafer, since the semiconductor substrate is not a fully rigid body but an elastic body, the wafer may be subjected to elastic deformation depending on a supporting fashion of the wafer so that the force escapes and thus is not applied to the porous layer effectively. Similarly, when inserting what is like a razor blade from the wafer end surface, unless the razor blade is fully thin and fully high in rigidity, the yield may be lowered.
Further, if the bonding strength at the bonded interface is weaker as compared with the strength of the porous Si layer or if weak portions exist locally, the two wafers may be separated at the bonded interface so that the initial object cannot be achieved.
Further, since, in any of the methods, the position where separation occurs in the porous layer is not fixed, if the ratio in etching speed between the porous Si and the bulk Si is not sufficient, the epitaxial silicon layer is first etched more or less at a portion where the porous layer remains thin rather than at a portion where the porous layer remains thick. Thus, the thickness uniformity of the SOI layer may deteriorate. Particularly, when the final thickness of the SOI layer is reduced to about 100 nm, the thickness uniformity is deteriorated so that a problem may result when forming the element, such as the fully depleted MOSFET, whose threshold voltage is sensitive to the film thickness.
Japanese Patent Application No. 5-211128 (corresponding to U.S. Pat. No. 5,374,564) discloses a method for producing the SOI. In this method, hydrogen ions are directly implanted into a single-crystal Si substrate, and then the single-crystal Si substrate and a support substrate are bonded together. Finally, the single-crystal Si substrate is separated at a layer where hydrogen ions are implanted, so as to form the SOI. In this met hod, since hydrogen ions are directly implanted into the single-crystal Si substrate which is then separated at the ion-implanted layer, the flatness of the SOI layer is not good. Further, the thickness of the SOI layer is determined by the projection range, so that the degree of freedom of the thickness is low. Further, it is necessary to select an implanting condition satisfying both the layer thickness and the separation, which creates a difficulty in control. Further, in case of aiming at obtaining a thin layer, the thickness of which cannot be determined by the ion implantation, it is necessary to carry out a reducing process in thickness such as grinding and etching, which process is nonselective, so that there is a fear of deteriorating uniformity of the thickness.
In view of the foregoing, a method has been demanded for producing, with high reproducibility, a high quality SOI substrate and whose SOI layer is extremely flat, while simultaneously saving resources and reducing costs through recycling of the wafer.
On the other hand, in general, on a light transmittable substrate, typically glass, the deposited thin Si layer only becomes amorphous or polycrystalline at best, reflecting disorderliness in crystal structure of the substrate, so that a high-performance device cannot be produced. This is due to the crystal structure of the substrate being amorphous, and thus an excellent single-crystal layer cannot be achieved by merely depositing the Si layer.
The light transmittable substrate is important for constituting a contact sensor as being a light-receiving element or a projection-type liquid-crystal image display device. To achieve further densification, higher resolution and increased fineness of picture elements of the sensor or the display device, a high-performance drive element is required. As a result, it is necessary to produce the element on the light transmittable substrate using the single-crystal layer having an excellent crystalline property.
Further, when using the single-crystal layer, reduction in size and acceleration of a chip can be achieved by incorporating a peripheral circuit for driving the picture elements and an image processing circuit into the same substrate having the picture elements.
Specifically, in case of amorphous Si or polycrystalline Si, it is difficult, due to its defective crystal structure, to produce the drive element having the performance which is required or will be required in the future.
On the other hand, to produce the compound semiconductor device, the substrate of the compound semiconductor is essential. However, the compound semiconductor substrate is expensive and further is very difficult to increase in area.
An attempt has been made to achieve the epitaxial growth of the compound semiconductor such as GaAs on the Si substrate. However, due to differences in lattice constant or thermal expansion coefficient, the grown film is poor in crystalline property and thus is very difficult to apply to the device.
Further, an attempt has been made to achieve the epitaxial growth of the compound semiconductor on porous Si to reduce misfit of the lattice. However, due to low thermostability and age deterioration of porous Si, its stability and reliability are poor as the substrate during or after production of the device. However, there is a problem that the compound semiconductor substrate is expensive and low in mechanical strength so that the large-area wafer is difficult to produce.
In view of the foregoing, an attempt has been made to achieve the heteroepitaxial growth of a compound semiconductor on a Si wafer which is inexpensive and high in mechanical strength so that a large-area wafer can be produced.
Recently, attention has been given to porous silicon as a luminescent material for photoluminescence, electroluminescence or the like, and many research reports have been made. In general, the structure of porous silicon largely differs depending on the type (p, n) and the concentration of impurities contained in the silicon. When the p-type impurities are doped, the structure of porous silicon is roughly divided into two kinds depending on whether the impurity concentration is no less than 10.sup.18 /cm.sup.3 or no more than 10.sup.17 /cm.sup.3. In the former case, the pore walls are relatively thick, that is, form several nanometers to several tens of nanometers, the pore density is about 10.sup.11 /cm.sup.2 and the porosity is relatively low. However, it is difficult for this porous silicon to luminescence. On the other hand, in the latter case, as compared with the former case, porous silicon whose pore wall is no more than several nanometers in thickness, whose pore density is greater by one figure order of magnitude and whose porosity exceeds 50%, can be easily formed. Most luminous phenomena, such as photoluminescence, are mainly based on the formation of porous silicon using the latter as a starting material. However, the mechanical strength is low due to the large porosity. Further, since a lattice constant deviation relative to bulk Si is as much as 10.sup.-3 (about 10.sup.-4 in the former case), there has been a problem that, when epitaxial-growing the single-crystal silicon layer on such porous silicon, defects are largely introduced into the epitaxial Si layer and cracks are further introduced thereinto. On the other hand, for utilizing the fine porous structure, which is suitable for a luminescent material, as a luminescent element, it has been desired that the epitaxial Si layer be formed on porous silicon for providing a contact or the MOSFET or the like as a peripheral circuit to be formed on the epitaxial silicon layer.